Non-volatile semiconductor memories are devices that can be electrically erased and reprogrammed. One type of non-volatile memory that is widely used for general storage and transfer of data in and between computers and other electronic devices is flash memory, such as a split gate flash memory. A split gate flash memory transistor has an architecture similar to that of a conventional logic transistor, such as Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), in that it also includes a control gate formed over a channel connecting a source and drain in a substrate. However, the memory transistor further includes a charge trapping layer between the control gate and the channel and insulated from both by insulating or dielectric layers. A programming voltage applied to the control gate traps a charge on the charge trapping layer, partially canceling or screening an electric field from the control gate, thereby changing a threshold voltage (VT) of the transistor and programming the memory cell. During read-out, this shift in VT is sensed by the presence or absence of current flow through the channel with application of a predetermined read-out voltage. To erase the memory transistor, an erase voltage is applied to the control gate to restore, or reverse the shift in VT.
An important measure of merit for flash memories is data retention time, which is the time for which the memory transistor can hold charge or remain programmed without the application of power. The charge stored or trapped in the charge trapping layer decreases over time due to leakage current through the insulating layers, thereby reducing the difference between a programmed threshold voltage (VTP) and an erased threshold voltage (VTE) limiting data retention of the memory transistor. Up until this time, efforts to improve data retention have focused on engineering of band-gaps of materials of the charge storage and insulating layers to increase charge trapping and/or reduce leakage current. However there are several fundamental problems with this approach.
One problem is that as semiconductor memories and their associated memory transistors continue to scale to smaller geometries it becomes increasingly difficult to control composition and thickness of the charge storage and insulating layers to achieve desired data retention time.
Another problem is that increasingly semiconductor memories combine logic transistors, such as MOSFET's, with memory transistors in integrated circuits (ICs) fabricated on a common substrate for embedded memory or System-On-Chip (SOC) applications. Many of the current processes for improving performance of memory transistors through band-gap engineering are incompatible with those used for fabricating logic transistors.
Finally, the current band-gap engineering processes do nothing to improve the speed or efficiency, measured as a function of the programming voltage or power applied to the control gate, with which the memory transistors are programmed.
Accordingly, there is a need for memory transistors and methods of forming the same that provides improved data retention, and increased programming speed and efficiency. It is further desirable that the methods of forming the memory device are compatible with those for forming logic elements in the same IC formed on a common substrate.